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RM0008
10.4
Note:
10.4.1
DMA controller (DMA)
DMA registers
Refer to Section 1.1 on page 37 for a list of abbreviations used in the register descriptions.
In the following registers, all bits relative to channel6 and channel7 are not relevant for
DMA2 since it has only 5 channels.
DMA interrupt status register (DMA_ISR)
Address offset: 0x00
Reset value: 0x0000 0000
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
TEIF7
HTIF7
TCIF7
GIF7
TEIF6
HTIF6
TCIF6
GIF6
TEIF5
HTIF5
TCIF5
GIF5
Reserved
r
r
r
r
r
r
r
r
r
r
r
r
15
TEIF4
r
14
HTIF4
r
13
TCIF4
r
12
GIF4
r
11
TEIF3
r
10
HTIF3
r
9
TCIF3
r
8
GIF3
r
7
TEIF2
r
6
HTIF2
r
5
TCIF2
r
4
GIF2
r
3
TEIF1
r
2
HTIF1
r
1
TCIF1
r
0
GIF1
r
Bits 31:28
Reserved, always read as 0.
Bits 27, 23, 19, 15, TEIFx: Channel x transfer error flag (x = 1 ..7)
11, 7, 3
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer error (TE) on channel x
1: A transfer error (TE) occurred on channel x
Bits 26, 22, 18, 14, HTIFx: Channel x half transfer flag (x = 1 ..7)
10, 6, 2
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No half transfer (HT) event on channel x
1: A half transfer (HT) event occurred on channel x
Bits 25, 21, 17, 13, TCIFx: Channel x transfer complete flag (x = 1 ..7)
9, 5, 1
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No transfer complete (TC) event on channel x
1: A transfer complete (TC) event occurred on channel x
Bits 24, 20, 16, 12, GIFx: Channel x global interrupt flag (x = 1 ..7)
8, 4, 0
This bit is set by hardware. It is cleared by software writing 1 to the corresponding bit in the
DMA_IFCR register.
0: No TE, HT or TC event on channel x
1: A TE, HT or TC event occurred on channel x
Doc ID 13902 Rev 9
191/995
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